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-- Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
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--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 10.1
--  \   \         Application : 
--  /   /         Filename : xil_2588_16
-- /___/   /\     Timestamp : 10/08/2008 23:59:07
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: 
--Design Name: 
--

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity sensor_sEMG is
   port ( EMG_superficial : in    std_logic_vector (15 downto 0); 
          EMG_amp_filt    : out   std_logic_vector (15 downto 0));
end sensor_sEMG;

architecture BEHAVIORAL of sensor_sEMG is
begin
end BEHAVIORAL;


